This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
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And doing it the other way around would have preserved more of the (precious) reserved C opcode space and all cores (including rocket) would be backwards compatible, because accepting illegal insn as legal is always okay. (Because it might as well be a custom vendor extension.)
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It was reverted, following the discussion
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