This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
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Just a side issue: I believe you have “no incompatible changes” backwards. The goal is for old software to work on new CPUs, not for old CPUs to run new software. Reserved opcodes are always intended to be able to be used in later specs, not illegal forever.
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What you mean is for new extensions. E.g. RV32I code should run on an RV32IM machine. But within an extension backward compatibility goes both ways. If I make a RV32I core now it should be able to execute RV32I code generated by a compiler 10 years from now.
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This particular change may be pointless, wrongheaded (and now reverted) but it does *not* break the backwards compatibility promise.
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