This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
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Thanks. Twitter will use this to make your timeline better. UndoUndo
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Tell me if I'm missing something, but wouldn't using the 24 reserved code points for XBitmanip also be a backwards-incompatible change?
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No, because Xbitmanip is an ISA extension RV32IC and RV32IC_Xbitmanip are two different ISA. This is not proposing to change the frozen RV32IC ISA.
End of conversation
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