This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
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Rocket of course used to be out of spec up to and including v2.2 of the spec. Starting with v2.3 rocket will magically be in spec and every other implementation that did it correct before will suddenly be in violation of the spec. Nothing matters.
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For what it's worth:https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/oT1r-owKicY …
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I'm starting to see how with chisel one can absorb changes like this more easily
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