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This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
I used to have a formally verified correct RISC-V core. With the release of v2.3 it will be out of spec. What happened to no backwards incompatible changes after v2.0? What happened to spike is the executable golden reference? It's all lies..
Rocket of course used to be out of spec up to and including v2.2 of the spec. Starting with v2.3 rocket will magically be in spec and every other implementation that did it correct before will suddenly be in violation of the spec. Nothing matters.
For what it's worth:https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/oT1r-owKicY …
Why is that important?
Because it means that valid code that compilers might generate for v2.3 and latter of the spec will trigger an illegal instruction trap on the processors that implemented the old version of the spec correctly.
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