A (minor) design flaw in RISC-V imo is the size of the floating point register file: 32 fregs is too many, 16 would have sufficed. We wouldn't need 4 major opcodes for fused multiply-add and it would be easier to find encoding space for non-ieee float insns (posits, packed simd).
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Coming back to this discussion. Yes, my statement was essentially assuming that if one has vector workloads that one is either using vector extension (spearate vector regs) or a (future) simd extension (using much wider fregs).
And simd is the main reason for my concern: This will require a myriad of instructions addressing fregs, so compact encoding of freg addresses matters. Also: having 32 possibly very wide fregs costs a lot of area. SSE for example has only 8 registers if I remember correctly..