Feel free to add your list of reasons why synthesis wouldn't match simulation on reddit: https://www.reddit.com/r/FPGA/comments/8g26i1/reasons_why_simulation_doesnt_match_synthesis/ … I'd like to collect the responses into a blog post.
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... or just handling of X's in general. "if (1'bx)" is false in simulation and essentially undetermined in synthesis.
Also: out-of bounds memory writes. Is ignored in simulation but usually overwrites the word at the address specified in the lower address bits in the generated circuit.
