Feel free to add your list of reasons why synthesis wouldn't match simulation on reddit: https://www.reddit.com/r/FPGA/comments/8g26i1/reasons_why_simulation_doesnt_match_synthesis/ … I'd like to collect the responses into a blog post.
-
Toggle MUX: How X-Optimism Can Lead to Malicious Hardware. Christian Krieg, Clifford Wolf, Axel Jantsch, and Tanja Zseby Proceedings of the 54th Annual Design Automation Conference 2017 (DAC '17) http://www.clifford.at/papers/2017/togglemux/dac2017_paper.pdf …
... or just handling of X's in general. "if (1'bx)" is false in simulation and essentially undetermined in synthesis.
-
-
Thanks,
@oe1cxw ! I'd forgotten about these issues.Thanks. Twitter will use this to make your timeline better. UndoUndo
-
-
-
Also: out-of bounds memory writes. Is ignored in simulation but usually overwrites the word at the address specified in the lower address bits in the generated circuit.
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.