A (minor) design flaw in RISC-V imo is the size of the floating point register file: 32 fregs is too many, 16 would have sufficed. We wouldn't need 4 major opcodes for fused multiply-add and it would be easier to find encoding space for non-ieee float insns (posits, packed simd).
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That seems like a big waste to me. How much code ever changes the rounding mode from default at all? I suspect it’s only there because the bits are available.
Idk. Without those bits fused multiply-add would only occupy half of a major opcode instead of four major opcodes. Not exactly my definition of "bits available" tbh.
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Yes and I don’t know how much use those static rounding modes get. Maybe they’re important in getting full accuracy with good performance in transcendental functions? But in that case, where is the support for things like argument range reduction and adjusting exponent fields?
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