A (minor) design flaw in RISC-V imo is the size of the floating point register file: 32 fregs is too many, 16 would have sufficed. We wouldn't need 4 major opcodes for fused multiply-add and it would be easier to find encoding space for non-ieee float insns (posits, packed simd).
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Anyway I don’t see this as an issue for RISC-V given that there is not only a lot more free space available in the 32 bit encoding than other RISCs (just look at Aarch64!), but also the entire 48 bit, 64 bit and larger encodings.
