A (minor) design flaw in RISC-V imo is the size of the floating point register file: 32 fregs is too many, 16 would have sufficed. We wouldn't need 4 major opcodes for fused multiply-add and it would be easier to find encoding space for non-ieee float insns (posits, packed simd).
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I don’t have anything immediately to hand (my Hennessy & Patterson is 1200 km away) but I’m sure this has been studied. FMAD takes a lot of space, yes, if the destination is encoded independently. The rest not so much.
3 bit rounding mode in each instruction also adds a lot to the space occupied by fp instructions.. (but also adds brownfield that can be used for float representations that do not require rounding modes, such as posits)
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That seems like a big waste to me. How much code ever changes the rounding mode from default at all? I suspect it’s only there because the bits are available.
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Idk. Without those bits fused multiply-add would only occupy half of a major opcode instead of four major opcodes. Not exactly my definition of "bits available" tbh.
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Anyway I don’t see this as an issue for RISC-V given that there is not only a lot more free space available in the 32 bit encoding than other RISCs (just look at Aarch64!), but also the entire 48 bit, 64 bit and larger encodings.
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Well I said in the OP that it is only a minor issue.
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