A (minor) design flaw in RISC-V imo is the size of the floating point register file: 32 fregs is too many, 16 would have sufficed. We wouldn't need 4 major opcodes for fused multiply-add and it would be easier to find encoding space for non-ieee float insns (posits, packed simd).
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One of the problems with 32 registers, floating point or otherwise, is that you still need to save them on any function call. If you are just going to stuff them on the stack anyway, you might find 16 is just as good.
At least for GPRs the risc-v ABI makes a distinction between caller-saved and callee-saved registers. Most small functions can be implemented and called without saving any registers.