I think it’s probably the other way around. Sixteen registers is usually plenty for integer code, but floating point code can often use all the registers you’ve got. (That might change if you have a vector unit)
A (minor) design flaw in RISC-V imo is the size of the floating point register file: 32 fregs is too many, 16 would have sufficed. We wouldn't need 4 major opcodes for fused multiply-add and it would be easier to find encoding space for non-ieee float insns (posits, packed simd).
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I believe that one can easily use all the fp regs available, but does it make a performance difference? (I don't have any data on this, so this is not a rethorical question. :) The cost in terms of instruction encoding space is big imo. Also the area cost of regs file for simd.
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I agree with Bruce regards floating point register usage and computational kernels. By many accounts FP kernels can use lots of registers. However regards round mode. rm is normally set with frm. It’s unnecessary per instruction as C11 FP ops use ‘dyn’ (111) which read frm.
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I think the only way to use static round mode is with inline asm.
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