@oe1cxw found a Verilog code which performs bad if synthesized within Vivado and perfectly with yosys (from git). Will share with you tmrw. RTL Sim is 1:1 same
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Nobody remembers when one's product works -- it's a means to an end. Everybody remembers when one's product fails, because it keeps them from their ends. *ponders* That's why I try to put far more effort into making it right when it's wrong than making it right when it's nothing.
The problem with Vivado is not that it occasionally displays a bug. The problem is that @XilinxInc is not fixing them! I have easy to reproduce and easy to fix segfault bugs with CR numbers that are *years* old now. They just don't care.
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Indeed. and they should -- it's also why open source/free software is so important for engineering/creative tools. It's really annoying when you can't modify what you have to use to create things with -- especially when they're broken!
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To be fair, at least it's not ISE. I've run in to multiple issues of this style in ISE and they drove me freaking nuts.
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