@oe1cxw found a Verilog code which performs bad if synthesized within Vivado and perfectly with yosys (from git). Will share with you tmrw. RTL Sim is 1:1 same
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My new Vivado 2017.4 favourite meme
#yosys@oe1cxw@ico_TC@fpga_davepic.twitter.com/NxspidSuLp
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Vivado is some of the buggiest software of any kind that I've ever encountered.
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Its the best commercially supported propriety bitstream generating FPGA software there is! Thousands of families depend on it.
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Vivado is not a total hell. As
@ico_TC always says the frustration is when you submit a bug report and it does not receive the expected attention3 replies 1 retweet 3 likes -
I've certainly found Vivado better than Quartus or Diamond in terms of buginess and overall usability
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