@oe1cxw found a Verilog code which performs bad if synthesized within Vivado and perfectly with yosys (from git). Will share with you tmrw. RTL Sim is 1:1 same
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They didn't even want our bug reports. Our company was too small for them to bother with apparently. We were directed to the forums. Only the large tier 1 companies got to submit bugs.
Here is a secret: You get to submit them. But that doesn't mean they fix them... I have an extremely simple to fix bugs that is so simple to fix, I can patch it in their asm! Have a CR tracking number and everything and they do not fix it for years now.
