Found some other big bugs, for example the divide instruction wasn't waiting for the multiply instruction to complete before issue. (Why would any one follow a multiply immediately with a divide?--wasn't in my test bench) I added these to the list in http://zipcpu.com/blog/2018/04/02/formal-cpu-bugs.html …
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Sure! I've got several test cases/programs that (apparently) aren't complete either. Tell me, though, wouldn't you rather be able to formally prove the CPU against *all* instruction mixes?
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What do you consider all instruction mixes? For non-trivial designs I imagine this is quite a few sequential instructions.
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FV is *exhaustive* for N (user def'd) cycles. That includes *all* sequential insn possibilities and *all* pipeline states of CPU. W/ induction, it becomes possible to prove (for sufficient N) *all* of those "quite a few" combinations of "sequential insns" you mention above
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I’m impressed at what you’ve done with formal verification. But don’t you quickly run into combinational explosion? eg. RISCV32IM is ~40 instructions. With sequence of 8 you have around 6.5 trillion permutations without considering pipeline or reg. Or is seq of 8 more than req?
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That's why you use SAT and SMT solvers instead of iterating over all possibilities https://en.wikipedia.org/wiki/Boolean_satisfiability_problem ….
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Thanks. I’m clearly going to have to get my head around this properly and try it myself. Is http://www.clifford.at/papers/2017/smtbmc-sby/slides.pdf … a good place to start?
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I like to think so. It has some nice examples that should help get you started.
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There's also a variety of articles on http://zipcpu.com discussing FV, starting from an introduction, and then moving to properties of a WB bus, a simple prefetch, a more complex prefetch, and an exercise illustrating how induction does (or doesn't) work.
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