I have not the slightest idea what people expect when they open a github issue with a bunch of copy&pasted error messages, but not the input that produced those errors. How can they not realize that they are just wasting the time of everyone involved?
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On this topic, is there an open-source Verilog test case minimizer (in the same spirit as creduce)?
You can use delta (http://delta.tigris.org/ ). Or just use creduce. @johnregehr keeps telling me it should work on non-C input as well..
