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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 31 Mar 2018
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      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩 Retweeted Greg

      cc @latticesemi: Reasons people use iCE40 FPGAs.https://twitter.com/GregDavill/status/979883322389098497 …

      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩 added,

      Greg @GregDavill
      Replying to @mithro @ico_TC and 2 others
      The open source toolchain/utilites. Physically a small FPGA (8x8mm). Enough IO for the application.
      2 replies 14 retweets 42 likes
    2. datenwolf – 𓍘𓅱𓀁𓇋𓄿𓅱𓀗‏ @datenwolf 31 Mar 2018
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      Replying to @oe1cxw @latticesemi

      @latticesemi indeed. When I learnt that there is a feature complete open source toolchain for iCE40 FPGAs I actually did the extra legwork of replacing all the @XilinxInc Spartan FPGAs in it (three Spartan-3, one Spartan-6). Having an open toolchain is such a strong incentive!

      1 reply 6 retweets 26 likes
    3. datenwolf – 𓍘𓅱𓀁𓇋𓄿𓅱𓀗‏ @datenwolf 31 Mar 2018
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      Replying to @datenwolf @oe1cxw and

      Just notices I ran out of characters up there. It's missing a "in a current project …"

      1 reply 0 retweets 1 like
    4. Dimitar Tomov‏ @tomov_eu 31 Mar 2018
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      Replying to @datenwolf @oe1cxw and

      Could you link to product page? Some of the ones you mentioned

      2 replies 0 retweets 0 likes
    5. datenwolf – 𓍘𓅱𓀁𓇋𓄿𓅱𓀗‏ @datenwolf 31 Mar 2018
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      Replying to @tomov_eu @oe1cxw and

      On a side note – and not really relevant for my decision: A pretty neat feature of the iCE40 family is, that you can actually "burn" program them. I.e. they have one-time-programmable configuration memory. Useful if you have a thorougly tested design and want it to be instant-on.

      1 reply 1 retweet 1 like
    6. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 31 Mar 2018
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      Replying to @datenwolf @tomov_eu and

      jfyi: It's *not* instant-on. The device still transfers the configuration data from NVCM to SRAM during power-on.

      1 reply 1 retweet 1 like
    7. datenwolf – 𓍘𓅱𓀁𓇋𓄿𓅱𓀗‏ @datenwolf 31 Mar 2018
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      Replying to @oe1cxw @tomov_eu and

      Thanks for the clarification. How many µs?

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 31 Mar 2018
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      Replying to @datenwolf @tomov_eu and

      Depends on the bitstream size and the "internal oscillator frequency" setting contained in the bitstream header. The bitstream size in turn not only depends on the device type but also on whether the bitstream includes bram init data (and how much of it).

      5:20 AM - 31 Mar 2018
      1 reply 0 retweets 0 likes
        1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 31 Mar 2018
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          Replying to @oe1cxw @datenwolf and

          But all this equally effects the initialization time when loading from an external SPI flash in SPI master mode. So I would expect the power-on period to be about equal when using an external SPI flash or the built-in NVCM.

          0 replies 1 retweet 1 like
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