A little preview of Chipy, a Python API for creating Verilog code generators. (PM me for the link to the svn repo.)pic.twitter.com/0mgf8ra61o
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Would be interesting to hear your thoughts on how a python hdl should be. The thing I find confusing about myhdl is that regs and wires are Signals, but not sure if that's just me. I'd be interested in a hdl that combines fpga design and pcb netlist generation.
Chipy essentially was meant as my contribution to this discussion. (What should a Python embedded HDL look and feel like.) I guess it still is (or can be). There are a few examples in the SVN repo, but I originally wanted to build a RISC-V core as demo project. But no time..