Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

I'd be very interested in how small you could make a RISC-V CPU on an FPGA. @oe1cxw PicoRV32 is a start but I feel things could go smaller - specially if performance was not an issue. I think the winner would be something like an 8-bit CPU running an emulator for @risc_v

In fact, I would probably be even willing to put up some prize money (or hardware) but don't have the bandwidth to run the "competition" myself...

How do you measure size? Number of LUTs? Is block RAM free?

I'd probably go with number of tiles or possibly config frames on Artix 7, with categories something along line of SLICEL only, SLICEL+SLICEM and "free for all" (DSP+BlockRAM). Figuring out the rules and how to evaluate entries is a large part of the effort I think?

Number of tiles and number of frames are *very* different metrics! A bram column contains 28+128=156 frames and 10 tiles. A logic column contains 36 frames and 50 tiles. So either a bram column is 4x *more* expensive than logic (frames) or 5x *less* expensive (tiles).

Related: In the free-for-all category, have points for "worst abuse of hard IP". Example: using a GP_COUNT8 with count=1 as a R-S FF (RST=R, CLK=S) when you run out of flipflops

What I /think/ I'm after is a RISC-V processor which is small enough that dedicating a whole core/CPU to doing bitbanging I2C or other similar low speed peripheral makes sense. RISC-V because of existing tooling for C programming.