Random crazy idea: Hardware demoscene. How small can you make a piece of RTL that does something cool? We could have "1K gate demos" etc.
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What I /think/ I'm after is a RISC-V processor which is small enough that dedicating a whole core/CPU to doing bitbanging I2C or other similar low speed peripheral makes sense. RISC-V because of existing tooling for C programming.
i2c is between 100 kbit/s and 3.2 Mbit/s. You won't be able to bitbang that on a core that takes up to hundreds of cycles for each RISC-V instruction. But you'd probably have performance like that with "an 8-bit CPU running an emulator for RISC-V", as you suggested.
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A thing I sometimes wonder about: Hardware running code as generated by https://github.com/xoreaxeaxeax/movfuscator … should be very easy to build and would be pretty small if you don't include memory in the resource metric.
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If the 8-bit CPU is running at 100MHz (ops) and 100 ops per instruction that is still 1MHz CPU which feels fast enough to bit bang I2C at 100kbit/s? On the RISC-V - I would actually be fine with any architecture that has mainline GCC support.
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AVR has good GCC/G++ support, partly because of Arduino and also because it has architecture designed with C in mind. There are already some AVR-compatible FPGA softcores out there, not sure what the legal situation is with them though (trademarks etc)
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(Ignore that I said it's boring a few days ago) I did the framework for an 8-bit CPU emulating RISC-V yesterday; gonna go ahead and agree w/ Clifford here. I think fitting into ice401k is doable, but you have a nice tradeoff to make >>
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* 8-bit route: Have plenty of room for a RISC-V user program at the cost of "takes 10s-100s of cycles to execute single RISC-V instruction". * Take less time to execute instructions by using FPGA fabric/block RAM to speed up operating on 1 byte at a time, but less user prg space.
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