First VHDL I've writen in a long while - almost all of a GPS channel, going from acquiring to locked in 40ms. 50 bits per second BPSK data clearly visible. Now to add prompt/late code tracking...pic.twitter.com/K7K3hUu9s6
Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.
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First VHDL I've writen in a long while - almost all of a GPS channel, going from acquiring to locked in 40ms. 50 bits per second BPSK data clearly visible. Now to add prompt/late code tracking...pic.twitter.com/K7K3hUu9s6
How are we going to convince you to switch to Verilog so I can selfishly use your awesome stuff directly with @oe1cxw 's toolchain?
You're just looking for syntax help porting vhdl to verilig?
For VHDL to Verilog syntax is the easy bit. Style, idiom and subtle behaviors are the tricky ones. For example, adding differently sized unsigned and signed values.
SystemVerilog can ease the transition by making signed and unsigned typedefs, maybe even unions if you have a bus with both on it. http://www.sutherland-hdl.com/papers/2006-SNUG-Boston_standard_gotchas_presentation.pdf … is a good reference, search for signed.
Sadly, like VHDL, no real support for SystemVerilog in open source tools yet.
For #VHDL there could be ghdlsynth. Don’t know how ‘active’ it’s under development, but maybe worth a try.https://github.com/tgingold/ghdlsynth-beta …
From what I hear vhd2vl works okay-ish. https://github.com/ldoolitt/vhd2vl I know people who use it on production ("industry") VHDL code to run it in Verilator, so it should support a reasonable subset of VHDL.
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