@oe1cxw Is riscv-formal limited to cores written in Verilog, or could a core written in VHDL be verified?
You need a formal verification tool that supports VHDL. Riscv-formal itself doesn't care about the language your core is written in.
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@oe1cxw Is riscv-formal limited to cores written in Verilog, or could a core written in VHDL be verified?
You need a formal verification tool that supports VHDL. Riscv-formal itself doesn't care about the language your core is written in.
