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.@ico_TC Question: The 16MB SPI flash is used to program the FPGA chip, I'm assuming. However, I'm also guessing that it can be used to supply firmware for soft-core CPUs as well. How does this actually work? How do you avoid conflicts between these two use-cases?
What conflict would you expect? When the fpga is programmed the flash pins are regular IO pins. No conflict there because the logic that loads the config from flash is inactive. During programming of the flash the FPGA is held in reset. So no problem there either.
Awesome. That clarifies a lot for me, thanks! I guess my next steps are to figure out a good layout of my binary blobs in the flash image then, and recode the CPU reset logic to boot from a non-zero address.
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