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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Luke Valenty‏ @TinyFPGA 17 Feb 2018
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      Finally back in the lab/office! So much I want/need to do. First up: help @esden debug the USB bootloader on his new icebreaker bitsy design.pic.twitter.com/aral0TMCjA

      2 replies 3 retweets 22 likes
      Show this thread
    2. Piotr Esden-Tempski @esden@chaos.social‏ @esden 17 Feb 2018
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      Replying to @TinyFPGA

      YEY! Thank you for doing this! Let me know if you need additional data points or testing! You know where to find me :D

      1 reply 0 retweets 0 likes
    3. Luke Valenty‏ @TinyFPGA 17 Feb 2018
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      Replying to @esden

      I’m going to take a look at it with no changes first. Then I might take out the ESD protection component to try and reduce the differences between my boards and your board.

      1 reply 0 retweets 1 like
    4. Piotr Esden-Tempski @esden@chaos.social‏ @esden 17 Feb 2018
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      Replying to @TinyFPGA

      The traces I sent you last were with the ESD protection removed. Did not change much...

      2 replies 0 retweets 0 likes
    5. Piotr Esden-Tempski @esden@chaos.social‏ @esden 17 Feb 2018
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      Replying to @esden @TinyFPGA

      But please do all the changes you think might help... do not trust my test setup! :D

      1 reply 0 retweets 0 likes
    6. Luke Valenty‏ @TinyFPGA 17 Feb 2018
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      Replying to @esden

      So it looks like the weird analog-ish problems were due to the long wires on USB in your test setup. I don’t see any ringing, missing syncs, or prolonged end of packet signaling in my setup. Still not working yet, but making progress.

      1 reply 0 retweets 1 like
    7. Luke Valenty‏ @TinyFPGA 17 Feb 2018
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      Replying to @TinyFPGA @esden

      I have good news and bad news. The good news: it works! The bad news: it doesn't currently work with icestorm on the ICE40UP5K parts. I synthesized with iCEcube2 and it was only able to get 50MHz for clk_48mhz. I suspect icestorm is not meeting timing.pic.twitter.com/WvRLVRQnDc

      3 replies 0 retweets 4 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 17 Feb 2018
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      Replying to @TinyFPGA @esden

      Does icetime tell you it meets timing?

      3:46 PM - 17 Feb 2018
      • 1 Like
      • Piotr Esden-Tempski @esden@chaos.social
      1 reply 0 retweets 1 like
        1. New conversation
        1. Luke Valenty‏ @TinyFPGA 17 Feb 2018
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          Replying to @oe1cxw @esden

          It looks like its reporting a logic loop. I'm not quite sure how to find the source of the loop from the output though. I used the Lattice tools and took care of a couple latches I had. Didn't see any combi loops with their tools.pic.twitter.com/SBXPc7MVeE

          1 reply 0 retweets 1 like
        2. Luke Valenty‏ @TinyFPGA 17 Feb 2018
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          Replying to @TinyFPGA @oe1cxw @esden

          Could this be related to the tristate outputs on USB? It might look like a logic loop to icestorm since the design is transmitting and receiving on the same two USB IOs.

          1 reply 0 retweets 1 like
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