Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩 on Twitter: "Only this: https://t.co/qJxl8yYNfu But that's not a HyperRAM core. It's just a test design that plays a fixed signal pattern from a ROM to test basic communications with the HyperRAM chip (see https://t.co/vZd5trzp66 for the pattern generator). https://t.co/F67RA7JZdE… https://t.co/bmxrb5H1mu"

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‏ @oe1cxw

Replying to @Wallbraker

Only this: http://svn.clifford.at/handicraft/2017/icohramtst/ … But that's not a HyperRAM core. It's just a test design that plays a fixed signal pattern from a ROM to test basic communications with the HyperRAM chip (see http://libretto.py for the pattern generator).https://twitter.com/oe1cxw/status/845912212090880000 …

Claire Xen BLM @oe1cxw

HyperRAM write and read transactions. (Embedded logic analyzer on IcoBoard prototype with HRAM chip.) @ico_TC http://svn.clifford.at/handicraft/2017/icohramtst … pic.twitter.com/lIl4G8HpQX

4:19 AM - 15 Feb 2018

2 replies

1. Claire Xen BLM ‏ @oe1cxw 15 Feb 2018
  
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  Table 5.3 from HyperBus Specification (http://www.cypress.com/file/213356/download …). It is configurable and the default value is device dependent.pic.twitter.com/gavGGyyzdv
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1. Jakob Bornecrantz ‏ @Wallbraker 15 Feb 2018
  
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  Thanks, everything will help!
  
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