HyperRAM is a mistake. I got it working 100%, but wow what a travesty
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Here it is, 32byte fixed bursts. Datasheet is wrong, extra cycles are needed from launch to data latch. Maybe tomorrow i'll have Starfox2 booting from it.pic.twitter.com/3rSLRP2ZvW
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If I remember correctly the number of cycles can be configured and different chips may have different default values. Or something like that ... it's been a while since I wrote a HyperRAM IP core.
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Are/will any of those cores be available with a FOSS license?
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Only this: http://svn.clifford.at/handicraft/2017/icohramtst/ … But that's not a HyperRAM core. It's just a test design that plays a fixed signal pattern from a ROM to test basic communications with the HyperRAM chip (see http://libretto.py for the pattern generator).https://twitter.com/oe1cxw/status/845912212090880000 …
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