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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Luke Valenty‏ @TinyFPGA 13 Feb 2018
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      @mithro mentioned to me that Project X-Ray used the routing results to correlate with the bitstream to document the Xilinx 7-series FPGA bitstream. This means I need a decoded version of the design after place-and-route stage. I finally found ncd2ncl.exe.

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    2. Luke Valenty‏ @TinyFPGA 13 Feb 2018
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      ncd2ncl.exe reads the binary "Native Circuit Description" file with all the design, routing, and placement information; and dumps out the data in ASCII. I looked for this binary before and didn't find it. Turns out the Linux "find" command is more patient than I am.

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    3. Luke Valenty‏ @TinyFPGA 13 Feb 2018
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      Here's the routing information that gets output. I believe this is the information needed to document the ECP5 FPGA routing. Now I need to understand the routing->bitstream correlation algorithm done by @oe1cxw.pic.twitter.com/2o8udddl5B

      1 reply 0 retweets 9 likes
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    4. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Feb 2018
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      Replying to @TinyFPGA

      The algorithm is implemented in the "segmatch" tool in prjxray. Usage example:pic.twitter.com/yBTlNIDFzK

      1 reply 0 retweets 3 likes
    5. Luke Valenty‏ @TinyFPGA 14 Feb 2018
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      Replying to @oe1cxw

      Nice. I’ll have to take a closer look tonight to understand the input format.

      1 reply 0 retweets 1 like
    6. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Feb 2018
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      Replying to @TinyFPGA

      The "seg <name>" lines start a new "segment" section. You can for example create one segment per tile (thus create many segments from one bitstream), or you can treat the whole chip as one large segment (and analyse many bitstream files to get more than one segment). 1/

      1 reply 0 retweets 1 like
    7. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Feb 2018
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      Replying to @oe1cxw @TinyFPGA

      Within a segment you write "bit <bitname>" when that bit is present in the bitstream, or omit that line out for bits that aren't set. Finally write "tag <tagname> 1" for segments for which you know that feature <tagname> is activated. "Feature" could be a routing PIP for ex. 2/

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Feb 2018
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      Replying to @oe1cxw @TinyFPGA

      Write "tag <tagname> 0" for segments where you know that feature <tagname> is not enabled, and no other feature that may share the same bits are present. (Such as another routing PIP for the same destination net.) 3/

      9:08 AM - 14 Feb 2018
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      • Luke Valenty
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        1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Feb 2018
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          Replying to @oe1cxw @TinyFPGA

          Simply omit "tag <tagname> 0/1" for segments where you either don't know if the feature is active or not, or where another feature that possibly shares some of the same bits is active. That's it. Run "segmatch -help" for additional options. 4/4

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