When you consider the difficulty I had in finding this bug, http://zipcpu.com/zipcpu/2017/12/28/ugliest-bug.html …, just a couple assertions in my prefetch module would've spared me a lot of time later!
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”I don’t have time” is rather a asign of bad management and not an issue with how you write the code.
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Is this is a book? What's its title?
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SystemVerilog Assertions and Functional Coverage; Ashok B. Mehta; ISBN 978-1-4614-7323-7http://www.springer.com/fr/book/9781461473237 …
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Looks like a useful book to read. Title plz?
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SystemVerilog Assertions and Functional Coverage; Ashok B. Mehta; ISBN 978-1-4614-7323-7http://www.springer.com/fr/book/9781461473237 …
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Assertions are important, but there are times where you might prefer completing the RTL first, if you need to get an initial design to your PD group for floorplanning and size estimates, regardless of bugs.
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But definitely, assertions will always find a bug earlier in simulation time compared to a black box DV test that has to catch bugs by looking at external interfaces. And then, you still have to trace back from there to get to the root cause inside, many clock cycles earlier.
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Sounds very much like the same reasoning that is/was used against unittesting and integration testing and continuous integration...
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The same applies to hardware designs, aka HDL, but the argument seems to be that the house of cards will never be touched as soon as it is taped out so why bother…
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