@oe1cxw hey mate, how to I allow yosys to honour module parameters. I'm having an issue with the nested parameters in https://github.com/alangarf/apple-one/blob/master/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v#L28 … for example. I get `ERROR: Can not open file `` for \$readmemh at ../../../rtl/ram.v:38.`
The Yosys "read_verilog" command by default first evaluates all modules with their default parameters. Call "read_verilog" with -defer to prevent this. (This means you will need to call hierarchy with "-top <top_module>", otherwise no module will be elaborated.)
