Please send a link to any information you might have. I have a couple strategies in mind for the primitives, but I am not yet sure how to tackle the routing boxes.
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Replying to @TinyFPGA
This is much more
@oe1cxw's domain, but my understanding is that it basically involves creating large numbers of designs at a low level, using Vivado's TCL interface, and comparing the bitstreams. https://github.com/SymbiFlow/prjxray … I'm not sure what interface Diamond gives you2 replies 0 retweets 0 likes -
Replying to @fpga_dave @oe1cxw
From your description, my strategy is similar. I'm going to start with this python script to generate the files for now since it's obvious how to make it work. Will change to tighter integration with the tools if necessary/useful. Thanks for the link.
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Good luck! Reverse engineering FPGAs is such good fun.
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Replying to @fpga_dave @oe1cxw
Put some automated code together for templating primitives and generating bitstreams with different parameters. I think I have decoded the LUT4s in the slice at R2C2A. Was interesting to find combinations of LUT tables that don't get optimized away, but all the bits can be IDedpic.twitter.com/sizCKTv6fF
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Very nice! Should now be possible also to identify cell/tile locations in the bitstream by using different LUT and seeing where the tables end up.
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Replying to @fpga_dave @oe1cxw
yup, making some changes to do that now. hopefully the encoding doesn't change from slice to slice.
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going to start with a smaller 2x2 PFU area and see if I spot any patterns. right now my flow goes through synthesis and P&R and it will get slow with larger numbers of iterations.
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Dave 🏳️🌈 Retweeted Claire Xen 🏳️⚧️ 🏳️🌈 🧙🏻♀️ BLM 🏴 🚩
Sensible, you don't want your computer to end up like Clifford's XDhttps://twitter.com/oe1cxw/status/929750491679952896 …
Dave 🏳️🌈 added,
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Replying to @fpga_dave @oe1cxw
I'm veeeery jealous of that amount of compute power
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