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From the simulation traces I've been shown and the proposed patch it looks like VCS is (at least in some situations) using the LHS of an assignment to determine the signedness of the RHS expression. That is of course *not* how Verilog works. (See 5.5.1 of IEEE Std 1364-2005.)pic.twitter.com/eTSafVIAu4
I'd post a MCVE for this but of course I can't create one because I don't have access to a copy of VCS. Here is all the information I have: https://github.com/cliffordwolf/picorv32/issues/33 … https://github.com/cliffordwolf/picorv32/pull/53 ….
The issue is closed, do you still wants input here?
The issue is closed because this is not a bug in PicoRV32. It's a bug in VCS and therefore not my problem. But I still think it would be good to let @synopsys know that their tools seems to be broken.
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