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Does anyone have a license for @synopsys VCS and can report bugs? People are sending me patches for my open source IP cores to work around bugs in VCS handling of signed expressions. I'm not going to merge them. Fix VCS instead! Ugh!
From the simulation traces I've been shown and the proposed patch it looks like VCS is (at least in some situations) using the LHS of an assignment to determine the signedness of the RHS expression. That is of course *not* how Verilog works. (See 5.5.1 of IEEE Std 1364-2005.)pic.twitter.com/eTSafVIAu4
I'd post a MCVE for this but of course I can't create one because I don't have access to a copy of VCS. Here is all the information I have: https://github.com/cliffordwolf/picorv32/issues/33 … https://github.com/cliffordwolf/picorv32/pull/53 ….
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