I also started with VHDL and moved to Verilog. VHDL is much harder to make mistakes in for beginners. Once you know what you are doing, Verilog takes a lot less typing. I have no plans on going back to VHDL ( other than for old design maintenance ).
I also started with VHDL. But as soon as I learned a little bit Verilog I immediately switched and never looked back. It's not perfect but IMO much better than VHDL. (The better support in open source tools is also a big plus. Flamewar in 3, 2, .. :)https://twitter.com/anders_breakin/status/958088015511019521 …
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Also in the Verilog camp. I started with Verilog 25+ years ago and it's so deeply ingrained I can write it by heart. I've been using VHDL for the last 7 years or so and I still need to refer to examples and cheat sheets.
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Better open-source support for Verilog is definitely a huge win, but I still personally prefer VHDL.
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It really is much more type-safe and has more features - really it's more comparable to System Verilog, and most free tools don't support System Verilog.
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I don't prefer Ada syntax. So there you go.
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Syntax isn't that important. Type safety, though, is very important.
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As someone who used to work in EDA, we found VHDL to be much better specified and it's much better type-safety to be much easier to deal with...
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At one point I was doing HDL code generation (VHDL&Verilog) and customers were using linting tools on our output. Verilog had many linting problems we had to fix. VHDL, hardly any.
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I use verilog for work, but trying to build a new HDL (Pyrope) https://masc.soe.ucsc.edu/pyrope.html
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I'm learning Chisel myself.
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