I've been asked to give a 20 minutes presentation on Spectre and Meltdown this Tuesday (Jan 30): http://quintessenz.at/d/000100034598 Yes, I told them that I'm not really a processor security person. ¯\_(ツ)_/¯ Here are my slides: http://www.clifford.at/papers/2018/spectre/ … Constructive feedback is welcome.
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RE: Spectre Mitigations slide, I doubt that hidden L1 cache slots mitigate Spectre-esque attacks. Any speculative cache access side effects, such as coherence state transitions in other caches, NoC traffic, L3 cache churn, DRAM traffic, QPI to other sockets, may be measured.
The slide doesn't say that this is L1 only. This would either need to go through the entire cache hierarchy, or you'd need to not speculatively execute loads for stuff not already present in the higher caches that don't support clean rollback. (The latter is more realistic imo.)
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Yes (sorry). Spec load of line into local L1$ must not alter any cache line state of any other cache. But might still be able to measure the coherence message traffic that ensues (and any other action, such as DRAM access, DRAM row precharge, etc. that you permit for spec perf.)
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