**way** too much text on many slides, especially "Out-of-order execution in modern CPUs" and "Spectre Mitigations". for the cache explanation i'd use some picture of the hierarchy that shows (the data of) one cache line in various places.
I've been asked to give a 20 minutes presentation on Spectre and Meltdown this Tuesday (Jan 30): http://quintessenz.at/d/000100034598 Yes, I told them that I'm not really a processor security person. ¯\_(ツ)_/¯ Here are my slides: http://www.clifford.at/papers/2018/spectre/ … Constructive feedback is welcome.
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What
@stefanct said!
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I did the same in my company. Spent a bit more on the difference of micro-architecture and processor architecture. Also highlighted it's not ignorance, but the side effect of many years of performance boosts, and people should be expecting more of that kind..
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Nice paper. On the bright side, they didn't ask you to explain it in just 5 minutes.
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Have you seen my take on this? The Spectre variants (which are really two completely separate issues) go quite a bit beyond biting JS/JITs. They can be used cross-process in principle. IMO we will never get rid of Variant 1 via CPU fix, but 2,3 are doable. https://github.com/marcan/speculation-bugs …
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Info and presentation flow looks good - only suggestion might be to break up the most verbose slides, unless you're distributing paper printouts to many people.
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RE: Spectre Mitigations slide, I doubt that hidden L1 cache slots mitigate Spectre-esque attacks. Any speculative cache access side effects, such as coherence state transitions in other caches, NoC traffic, L3 cache churn, DRAM traffic, QPI to other sockets, may be measured.
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The basis of the problem is speculation x sharing. (Sharing also encompasses power and thermal budgets.) To preclude these problems, disallow speculation, or disallow shared resources, or disallow commingling of my software and untrusted software on shared resources.
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2x typos on slide "Spectre Mitigations": extend -> extent
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thanks. fixed.
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