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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 7 Jan 2018
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      FPGA Vendor documentation at it's best, iCE40 Ultra Plus edition. Left - Device datasheets (that same image is used in every relevant PDF) Right - Schematic of the official iCE40UP5K development board Extra WTF moment: There is no GNDPLL pin on that device.pic.twitter.com/XU1tsxXNtp

      5 replies 10 retweets 26 likes
    2. Dave  🏳️‍🌈‏ @fpga_dave 7 Jan 2018
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      Replying to @oe1cxw

      So it turns out I've been falsely blaming the UPDuino designers for this mistake, actually they just copied the dev board. I think the capacitor is needed though, unfiltered VccPLL would be odd.

      2 replies 0 retweets 4 likes
    3. Miodrag Milanovic‏ @micko_mame 7 Jan 2018
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      Replying to @fpga_dave @oe1cxw

      As I understood from info he provide, seams that author is Lattice engineer so this makes perfect sense.

      1 reply 0 retweets 2 likes
    4. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 7 Jan 2018
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      Replying to @micko_mame @fpga_dave

      Holy sh*t you are right! That guy seems to have 4 years of experience as Lattice AE according to his Linkedin profile.By the looks of it I thought the UPDuino board was designed by freshman student. (Highlighted net is GND. There is no ground fill. Bypass caps in yellow circles.)pic.twitter.com/AZUrCdPDcZ

      6 replies 1 retweet 9 likes
    5. andrea‏ @be17068 16 Jan 2018
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      Replying to @oe1cxw @micko_mame @fpga_dave

      you are both right and wrong! :-) https://www.element14.com/community/groups/fpga-group/blog/2017/09/30/gnarly-grey-upduino#comment-115883 … i suppose he's marketing guy..

      1 reply 0 retweets 2 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 16 Jan 2018
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      Replying to @be17068 @micko_mame @fpga_dave

      The "college kid" who made that board obviously doesn't understand the basic physics. No amount of "feedback" will fix that. Either he should get a proper board designer or make sure that that student at least has meanwhile completed the class where they teach loop inductance.pic.twitter.com/7q6LAPr5sJ

      8:51 AM - 16 Jan 2018
      1 reply 1 retweet 0 likes
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        2. Dave  🏳️‍🌈‏ @fpga_dave 17 Jan 2018
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          Replying to @oe1cxw @be17068 @micko_mame

          Interestingly, there's a PCB design (but no schematic or BOM) for the UPDuino 2.0 here. Looks to have a ground plane at least, and some kind of programming hardware - but decoupling still looks dubious https://www.pcbway.com/project/shareproject/W45302ASS8_upduino2_pcb.html …

          1 reply 0 retweets 2 likes
        3. Eric Brombaugh‏ @ebrombaugh 17 Jan 2018
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          Replying to @fpga_dave @oe1cxw and

          Augh! Fully SMT USB connector - no thru-hole tabs for mechanical stability. Those are the ones that peel off the board at the first opportunity...

          1 reply 0 retweets 1 like
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