So it turns out I've been falsely blaming the UPDuino designers for this mistake, actually they just copied the dev board. I think the capacitor is needed though, unfiltered VccPLL would be odd.
FPGA Vendor documentation at it's best, iCE40 Ultra Plus edition. Left - Device datasheets (that same image is used in every relevant PDF) Right - Schematic of the official iCE40UP5K development board Extra WTF moment: There is no GNDPLL pin on that device.pic.twitter.com/XU1tsxXNtp
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This whole thing is super confusing. R before C makes total sense for a low-current supply pin, but R after C? Why would anyone want that? Why would anyone deliberately want to turn dI into dV instead of minimizing dV?
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Nice find.
Thanks. Twitter will use this to make your timeline better. UndoUndo
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Waaait, they have a decoupling cap network and then a SERIES RESISTOR between it and the FPGA???
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Power consumption measurements?
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Shit. I would have read this thread before.
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Someone should probably tell Lattice about this too... It's beyond the pale how terrible an idea it is to put that circuit on an official breakout board
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