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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 2 Jan 2018
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      Creating spec for an iCE40UP5K development board. Please reply with your feedback: Anything important missing from that spec?pic.twitter.com/x4TKdVuKyd

      14 replies 8 retweets 32 likes
    2. andreasdotorg‏ @andreasdotorg 2 Jan 2018
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      Replying to @oe1cxw

      I might be an outlier, but... DRAM.

      2 replies 0 retweets 2 likes
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 2 Jan 2018
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      Replying to @andreasdotorg

      We have one MBit of SPRAM in the FPGA. The chip has only 39 IO pins, so external RAM isn't really an option.

      1 reply 0 retweets 0 likes
    4. andreasdotorg‏ @andreasdotorg 2 Jan 2018
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      Replying to @oe1cxw

      Ok, good enough reason.

      1 reply 0 retweets 1 like
    5. Jan Gray‏ @jangray 2 Jan 2018
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      Replying to @andreasdotorg @oe1cxw

      How about some Cypress 512Mb+64 Mb HyperFlash+RAM? ~15 pins? :-) http://www.cypress.com/file/322936/download … No experience, don't know if shipping yet, etc.

      1 reply 0 retweets 1 like
    6. Jan Gray‏ @jangray 2 Jan 2018
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      Replying to @jangray @andreasdotorg @oe1cxw

      Oh, I see the 39 IOs are already taken. It would be too much to ask to make the dual PMOD pins dual-use for the RAM. Sorry, nevermind.

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 2 Jan 2018
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      Replying to @jangray @andreasdotorg

      But could be interesting as a module for the dual PMOD port.

      5:22 PM - 2 Jan 2018
      • 1 Like
      • Jan Gray
      1 reply 0 retweets 1 like
        1. New conversation
        1. OSS FPGA & ASIC EDA tools‏ @ico_TC 3 Jan 2018
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          Replying to @oe1cxw @jangray @andreasdotorg

          There is the dual PMOD hyperRAM module from @bml_khubbard

          3 replies 0 retweets 4 likes
        2. Kevin Hubbard‏ @bml_khubbard 3 Jan 2018
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          Replying to @ico_TC @oe1cxw and

          I have one suggestion. Include 5V 0.100" header between dual-PMOD connectors. I am doing this standard now for all my FPGA boards and dual-PMOD peripheral boards. Providing unregulated 5V w/o current limits is beneficial for many designs ( esp quiet Analog boards needing 3V ).

          2 replies 0 retweets 2 likes
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