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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 2 Jan 2018
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      Creating spec for an iCE40UP5K development board. Please reply with your feedback: Anything important missing from that spec?pic.twitter.com/x4TKdVuKyd

      14 replies 8 retweets 32 likes
    2. andreasdotorg‏ @andreasdotorg 2 Jan 2018
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      Replying to @oe1cxw

      I might be an outlier, but... DRAM.

      2 replies 0 retweets 2 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 2 Jan 2018
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      Replying to @andreasdotorg

      We have one MBit of SPRAM in the FPGA. The chip has only 39 IO pins, so external RAM isn't really an option.

      5:24 AM - 2 Jan 2018
      1 reply 0 retweets 0 likes
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        1. andreasdotorg‏ @andreasdotorg 2 Jan 2018
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          Replying to @oe1cxw

          Ok, good enough reason.

          1 reply 0 retweets 1 like
        2. Jan Gray‏ @jangray 2 Jan 2018
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          Replying to @andreasdotorg @oe1cxw

          How about some Cypress 512Mb+64 Mb HyperFlash+RAM? ~15 pins? :-) http://www.cypress.com/file/322936/download … No experience, don't know if shipping yet, etc.

          1 reply 0 retweets 1 like
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