I might be an outlier, but... DRAM.
Creating spec for an iCE40UP5K development board. Please reply with your feedback: Anything important missing from that spec?pic.twitter.com/x4TKdVuKyd
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We have one MBit of SPRAM in the FPGA. The chip has only 39 IO pins, so external RAM isn't really an option.
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'245 async FIFO' compatible (8 Mbytes/sec) signals routed between FT2232 and FPGA would be nice if there is enough pin to spare. Definitely a step up from standard serial port speeds. People can fall back to standard UART via EEPROM. Also, thanks for all the work you are doing.
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No pins to spare. But we could add some zero ohm resistor footprints that would allow a user to easily repurpose some of the pmod pins for fifo mode.
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There are PMODs for that.
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test points for all power rails. Jumpers/zero ohm on all rails for consumption testing.
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That's a good one! Added to the spec.
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Tiny I2C accelerometer. Not much real-estate, can be used to check bus
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There are PMODs for that.
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