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Happy to announce SymbiFlow and Project X-Ray: https://symbiflow.github.io/ https://github.com/SymbiFlow/prjxray … Browse our Artix7 CLB+INT Bit-Stream Documentation: https://symbiflow.github.io/prjxray-db/artix7/ …pic.twitter.com/YybnJ4ogrX
That Artix-7 Bit-Stream Documentation is now also on the @internetarchive:
https://web.archive.org/web/20171221170307/https://symbiflow.github.io/prjxray-db/ …
https://web.archive.org/web/20171221170333/https://symbiflow.github.io/prjxray-db/artix7/ …
Limited to only one region of the FPGA!? I assume there is limited symmetry across regions. I realize modern FPGAs are not uniform, but I'm curious why you chose that particular region, and how hard might it be to relocate the bit interpretation across regions?
Afaict the bits in a tile type do not vary over the one device. I'm right now in the process of doing a Kintex-7 device for comparison. This is the default Artix-7 region of interest, but you can configure any region in the settings.sh file and re-run the scripts.
Very cool! Impressive work
Having names for each bit is great and all, but do you have docs on what the bits *do*? LUT INIT is obvious but in the case of say CLBLL_R.SLICEL_X0.ALUT.RAM does that mean 1 or 0 is RAM mode?
The names all describe what the bit does when it's set. So 1 is RAM mode. This is just a preliminary release. More to come.
Agreed. Great work.
Do you think there will be much difference with the Spartans? Will it work with them?
In the long term we wand to support all 7-Series, UltraScale, and UltraScale+ devices, as stated on the SymbiFlow website. So far I did not look into Spartan-7, but I expect it to use the same bit-stream format as Artix-7 and Kintex-7. (Timing might be different of course.)
Fantastic work! I have a @DigilentInc Genesys2 board with a XC7K325T-2FFG900C Kintex-7 #FPGA, and since it's the holidays, I'll have time to try to contribute as well.
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