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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Kevin Hubbard‏ @bml_khubbard 20 Dec 2017
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      BML's 12bit color DVI digital video PMOD board is now running on the Lattice ICE40 icoBoard. Didn't know how to synthesize a 40 MHz clock for SVGA 800x600, so this demo is at 1280x720 50 Hz with a 50 MHz dot clock. @ico_TC @oe1cxw https://blackmesalabs.wordpress.com/2017/12/15/bml-hdmi-video-for-fpgas-over-pmod/ …pic.twitter.com/LgDh487POj

      1 reply 9 retweets 21 likes
    2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 20 Dec 2017
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      Replying to @bml_khubbard @ico_TC

      What problem did you run into generating the 40 MHz clock? Should be easy to do from 100 MHz with the iCE40 PLL.

      1 reply 0 retweets 0 likes
    3. Kevin Hubbard‏ @bml_khubbard 20 Dec 2017
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      Replying to @oe1cxw @ico_TC

      I didn't run into any problems - I just didn't want to bother. I was going down the path of finding a resolution that I thought might display well on my 58" Samsung TV and found 1280x720x50 Hz with 50 MHz dot clock and I thought - "Hey - I can just throw this into the icoBoard!"

      2 replies 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 20 Dec 2017
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      Replying to @bml_khubbard @ico_TC

      I see. Just for your information, "icepll" makes it really easy using iCE40 PLLs:pic.twitter.com/9ghOacHpVp

      12:56 PM - 20 Dec 2017
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      • Piotr Esden-Tempski @esden@chaos.social Al Ravi Vijayakumar
      2 replies 1 retweet 3 likes
        1. Kevin Hubbard‏ @bml_khubbard 20 Dec 2017
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          Replying to @oe1cxw @ico_TC

          okay thanx. I'll give that whirl and add it to my toolkit of Lattice knowledge ( have I already mentioned I'm primarily a Xilinx guy? ). I'm still looking for a resolution that will display on my Samsung TV....

          0 replies 0 retweets 2 likes
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        2. Kevin Hubbard‏ @bml_khubbard 20 Dec 2017
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          Replying to @oe1cxw @ico_TC

          OK - working at 800x600 on icoBoard now with a PLL synthesized 40 MHz. Thanks! Don't have an ODDR flop for clock mirroring, but it seems to work okay just driving the clock tree out to a pin.

          1 reply 0 retweets 1 like
        3. Dave  🏳️‍🌈‏ @fpga_dave 21 Dec 2017
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          Replying to @bml_khubbard @oe1cxw @ico_TC

          You can use an SB_IO as a DDR output if needed, using D_OUT_0 and D_OUT_1 and setting PIN_TYPE correctly.

          0 replies 0 retweets 2 likes
        4. End of conversation

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