Ohh my glob. I have a 32-bit wide 10:1 mux implemented as a wired-or with enables. The optimal structure is 224 LUT4s and is only 3 LUTs deep. Synplify Pro implements it as 434 LUT4s and I can't even tell how deep it is.pic.twitter.com/gsMOFz6Y4q
Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.
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Ohh my glob. I have a 32-bit wide 10:1 mux implemented as a wired-or with enables. The optimal structure is 224 LUT4s and is only 3 LUTs deep. Synplify Pro implements it as 434 LUT4s and I can't even tell how deep it is.pic.twitter.com/gsMOFz6Y4q
Tech mapping trick: you can halve that if you can afford a pipeline stage: register the 10 32b inputs into 10 32b registers with resets. (0 LUTs, depending.) Decode the select to clear 9 of them each cycle. Build a 10-input 32-bit or-tree using 32x3 4LUTs.
I think a latch with reset should also work, in case one doesn't want to add a pipeline stage.
Do the iCE40 devices have true latches? I thought they just emulated latches with a flop and LUT (acting as a mux).
No latches on iCE40. But Jan is a Xilinx person so I was thinking more about Xilinx devices when I replied to his comment.
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