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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Luke Valenty‏ @TinyFPGA 2 Dec 2017
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      Ohh my glob. I have a 32-bit wide 10:1 mux implemented as a wired-or with enables. The optimal structure is 224 LUT4s and is only 3 LUTs deep. Synplify Pro implements it as 434 LUT4s and I can't even tell how deep it is.pic.twitter.com/gsMOFz6Y4q

      3 replies 2 retweets 10 likes
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    2. Jan Gray‏ @jangray 5 Dec 2017
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      Replying to @TinyFPGA

      Tech mapping trick: you can halve that if you can afford a pipeline stage: register the 10 32b inputs into 10 32b registers with resets. (0 LUTs, depending.) Decode the select to clear 9 of them each cycle. Build a 10-input 32-bit or-tree using 32x3 4LUTs.

      3 replies 0 retweets 6 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Dec 2017
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      Replying to @jangray @TinyFPGA

      I think a latch with reset should also work, in case one doesn't want to add a pipeline stage.

      2:48 PM - 5 Dec 2017
      • 2 Likes
      • Luke Valenty Dimitar Tomov
      1 reply 0 retweets 2 likes
        1. New conversation
        2. Luke Valenty‏ @TinyFPGA 5 Dec 2017
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          Replying to @oe1cxw @jangray

          Do the iCE40 devices have true latches? I thought they just emulated latches with a flop and LUT (acting as a mux).

          1 reply 0 retweets 0 likes
        3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Dec 2017
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          Replying to @TinyFPGA @jangray

          No latches on iCE40. But Jan is a Xilinx person so I was thinking more about Xilinx devices when I replied to his comment.

          0 replies 0 retweets 0 likes
        4. End of conversation

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