Listening to a panel discussion at SJSU about AI and deep learning. Suddenly the whole panel starts talking about RISC-V, but apparently none of them even seem to understand that RISC-V isn't an open source processor.
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Replying to @oe1cxw
Can you elaborate on your point ? - aren't there multiple RISC-V implementations ? Or are you drawing a distinction between open ISA and open impls
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Replying to @rbarris
RISC-V is an open ISA. It is flexible (32/64 bits, extensions for various application domains). There are many implementations some open source, some not. The people on this panel seem to think it is one open source processor.
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You could point them to https://www.esperanto.ai/
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Replying to @KeithMEvans @rbarris
Claire Xen 🏳️⚧️ 🏳️🌈 🧙🏻♀️ BLM 🏴 🚩 Retweeted Claire Xen 🏳️⚧️ 🏳️🌈 🧙🏻♀️ BLM 🏴 🚩
Claire Xen 🏳️⚧️ 🏳️🌈 🧙🏻♀️ BLM 🏴 🚩 added,
Claire Xen 🏳️⚧️ 🏳️🌈 🧙🏻♀️ BLM 🏴 🚩 @oe1cxw
.@EsperantoTech just came out of stealth mode. They're building a high performance (TeraFLOPs) RISC-V general purpose processor system with 16 cores optimized for single thread performance, and 4096 cores for parallel workloads (such as machine learning and graphics).
11:08 PM - 4 Dec 2017
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