Discuss: Which version is "better" and why? How would you solve this?pic.twitter.com/KLuwMPRsoo
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Can you replace the "i<10" with "i < sizeof(en)" or something, ready for the day when 'en' becomes 11 bits long? Otherwise, that has a very nice feel to it - far nicer than check_en_ref IMO.
Here is how I would build almost the same circuit in Verilog.
Yes, in SystemVerilog you can write "$bits(en)". This is supported by Yosys, but I'm not sure about other FOSS Verilog tools. Otherwise you can simply create a parameter and use that as size for "en" and in the loop condition. Like DEPTH in this code by @TinyFPGA.pic.twitter.com/wBsyuvb0ef
