Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

For ASIC synthesis they yield pretty much the same result because it's such a small circuit logic optimization just sees the whole function, so you say "check_en_alt" is best? (For iCE40 synth with icestorm "check_en" is smallest because in the other cases we get carry logic.)

So you are saying for you the only thing important is area after synthesis and other things like readability (or logic depth) are not important? Okay. Just to clarify: I was not asking for advise, I was trying to spur discussion about Verilog coding style and design decisions.

But would you instinctively understand what check_en_alt does if you would encounter that line of code? How long would it take you to convince yourself that it is correct?

I don't understand what you mean by "just an expansion of". They are three independent implementations of the same simple functionality.

check_en_alt would be the easiest for me, but only because I've seen the (x&(x-1)) == 0 trick before. A comment there would make it obvious for anyone else and IMO it's the easiest to verify.