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Ohh my glob. I have a 32-bit wide 10:1 mux implemented as a wired-or with enables. The optimal structure is 224 LUT4s and is only 3 LUTs deep. Synplify Pro implements it as 434 LUT4s and I can't even tell how deep it is.pic.twitter.com/gsMOFz6Y4q
What is Yosys doing? What Verilog code are you using to infer the structure?
I haven't yet taken a look at yosys synthesis output. Here are three different examples I've tried. I was trying these options to help with correct x-propagation, and not yet trying to get optimal synthesis results.https://gist.github.com/tinyfpga/fd214f30c2b4ac7d4a85ec17c43bb4f9 …
A few changes to try: 1. Extend enable signals to 32 bits and use all bitwise logic. 2: Construct logic structure in a tree rather than in a linear order. 3. Crest modules to mimic LUT4 structure and connect them. 4: use LUT4 primitives.
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